Top Posts

• [Top] Feb 12, 2023

  Understanding Redis Source Code

• [Top] Nov 20, 2022

  Cheat Sheet for Building and Deploying SPEC

• [Top] Mar 9, 2022

  QEMU Cheat Sheet for Full-System Simulation

• [Top] Jan 22, 2020

  Understanding Discrete Event Contention Simulation in zSim

• [Top] Jan 9, 2020

  Understanding Cache Coherence Concurrency Control Protocol in zSim

• [Top] Jan 1, 2020

  Understanding Processor Microarchitecture Simulation in zSim

• [Top] Dec 25, 2019

  Understanding Cache System Simulation in zSim

• [Top] Mar 16, 2018

  Adding Dynamic Github Contribution Calendar To Your Static Page

---




Posts

• [Paper Review] Aug 18, 2019 , Paper published in MICRO 2018

  CSALT: Context Switch Aware Large TLB

  Keyword: TLB; LRU; Cache Replacement
• [Paper Review] Aug 17, 2019 , Paper published in MICRO 2018

  Improving the Performance and Ensurance of Encrypted Non-Volatile Main Memory through Deduplicated Writes

  Keyword: NVM; Counter Mode Encryption; Deduplication
• [Paper Review] Aug 16, 2019 , Paper published in MICRO 2018

  STRAIGHT: Hazardless Processor Architecture Without Register Renaming

  Keyword: Register renaming; Straight; Microarchitecture
• [Paper Review] Aug 12, 2019 , Paper published in MICRO 2015

  A Scalable Architecture for Ordered Parallelism

  Keyword: Swarm; TLS; HTM; Speculation
• [Paper Review] Aug 10, 2019 , Paper published in MICRO 2018

  iDO: Compiler-Directed Failure Atomicity for Non-Volatile Memory

  Keyword: JUSTDO; iDO; Failure Atomicity; Idempotent Region

Subscribe via RSS

Switch to Small

Switch to All