Top Posts

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  Understanding Redis Source Code
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  Cheat Sheet for Building and Deploying SPEC
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  QEMU Cheat Sheet for Full-System Simulation
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  Understanding Discrete Event Contention Simulation in zSim
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  Understanding Cache Coherence Concurrency Control Protocol in zSim
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Posts

• [Paper Review]
  SpecFaaS: Accelerating Serverless Applications with Speculative Function Execution
• [Paper Review]
  Reducing DRAM Footprint with NVM in Facebook
• [Paper Review]
  Read-Log-Update: A Lightweight Synchronization Mechanism for Concurrent Programming
• [Paper Review]
  Delta pointers: buffer overflow checks without the checks
• [Paper Review]
  Cuckoo Trie: Exploiting Memory-Level Parallelism for Efficient DRAM Indexing
• [Paper Review]
  Wormhole: A Fast Ordered Index for In-memory Data Management
• [Paper Review]
  Bridging the Performance Gap for Copy-based Garbage Collectors atop Non-Volatile Memory
• [Paper Review]
  ResPCT: Fast Checkpointing in Non-volatile Memory for Multi-threaded Applications
• [Paper Review]
  FaaSnap: FaaS made fast using snapshot-based VMs
• [Paper Review]
  In-fat pointer: hardware-assisted tagged-pointer spatial memory safety defense with subobject granularity protection
• [Paper Review]
  PTEMagnet: fine-grained physical memory reservation for faster page walks in public clouds
• [Paper Review]
  CARAT CAKE: Replacing Paging via Compiler/Kernel Cooperation
• [Paper Review]
  MineSweeper: A Clean Sweep for Drop-In Use-after-Free Prevention
• [Paper Review]
  Libnvmmio: Reconstructing Software IO Path with Failure-Atomic Memory-Mapped Interface
• [Paper Review]
  Austere Flash Caching with Deduplication and Compression
• [Paper Review]
  FlatFS: Flatten Hierarchical File System Namespace on Non-volatile Memories
• [Paper Review]
  FlatStore: An Efficient Log-Structured Key-Value Storage Engine for Persistent Memory
• [Paper Review]
  Pacman: An Efficient Compaction Approach for Log-Structured Key-Value Store on Persistent Memory
• [Paper Review]
  Hardware-based Always-On Heap Memory Safety
• [Paper Review]
  ATTC (@C): Addressable-TLB based Translation Coherence
• [Paper Review]
  Enhancing Address Translations in Throughput Processors via Compression
• [Paper Review]
  Memory Deduplication for Serverless Computing with Medes
• [Paper Review]
  HTMFS: Strong Consistency Comes for Free with Hardware Transactional Memory in Persistent Memory File Systems
• [Paper Review]
  Page Size Aware Cache Prefetching
• [Paper Review]
  Translation-optimized Memory Compression for Capacity
• [Paper Review]
  DaxVM: Stressing the Limits of Memory as a File Interface
• [Paper Review]
  Cocoa: Synergistic Cache Compression and Error Correction in Capacity Sensitive Last Level Caches
• [Paper Review]
  Dual Dictionary Compression for the Last Level Cache
• [Paper Review]
  The reuse cache: downsizing the shared last-level cache
• [Paper Review]
  Dynamic Dictionary-Based Data Compression for Level-1 Caches
• [Paper Review]
  Frequent value compression in data caches
• [Paper Review]
  Cache Compression with Efficient in-SRAM Data Comparison
• [Paper Review]
  Making Huge Pages Actually Useful
• [Paper Review]
  Trident: Harnessing Architectural Resources for All Page Sizes in x86 Processors
• [Paper Review]
  Software-Defined Address Mapping: A Case on 3D Memory
• [Paper Review]
  EveryWalk’s a Hit: Making PageWalks Single-Access Cache Hits
• [Paper Review]
  Free Atomics: Hardware Atomic Operations without Fences
• [Paper Review]
  Lukewarm serverless functions: characterization and optimization
• [Paper Review]
  ASAP: Architecture Support for Asynchronous Persistence
• [Paper Review]
  NvMR: Non-Volatile Memory Renaming for Intermittent Computing
• [Paper Review]
  GBDI: Going Beyond Base-Delta-Immediate Compression with Global Bases
• [Paper Review]
  Exploiting Inter-block Entropy to Enhance the Compressibility of Blocks with Diverse Data
• Understanding Memory Hierarchy Simulation in SST
• Understanding Ariel Core Simulation in SST
• Understanding Simulation Infrastructure in SST
• Understanding TLB Simulation in Samba (SST)
• [Paper Review]
  Cerebros: Evading the RPC Tax in Datacenters
• [Paper Review]
  COSPlay: Leveraging Task-Level Parallelism for High-Throughput Synchronous Persistence
• [Paper Review]
  Architectural Implications of Function-as-a-Service Computing
• [Paper Review]
  FaaSM: Lightweight Isolation for Efficient Stateful Serverless Computing
• [Paper Review]
  Benchmarking, Analysis, and Optimization of Serverless Function Snapshots
• [Paper Review]
  Serverless in the Wild: Characterizing and Optimizing the Serverless Workload at a Large Cloud Provider
• [Paper Review]
  Peeking Behind the Curtains of Serverless Platforms
• [Paper Review]
  Serverless Computation with OpenLambda
• [Paper Review]
  FaaSCache: Keeping Serverless Computing Alive with Greedy-Dual Caching
• [Paper Review]
  Cloudburst: Stateful Function-as-a-Service
• [Paper Review]
  Serverless Computing: One Step Forward, Two Steps Back
• [Paper Review]
  SAND: Towards High-Performance Serverless Computing
• [Paper Review]
  Scalable Architectural Support for Trusted Software
• [Paper Review]
  Firecracker: Lightweight Virtualization for Serverless Applications
• [Paper Review]
  BabelFish: Fuse Address Translation for Containers
• [Paper Review]
  SOCK: Rapid Task Provisioning with Serverless-Optimized Containers
• [Paper Review]
  Catalyzer: Sub-Millisecond Startup for Serverless Computing with Initialization-Less Booting
• [Paper Review]
  SEUSS: Skip Redundant Paths to Make Serverless Fast
• [Paper Review]
  Put the "Micro" Back in Microservice
• [Paper Review]
  Nightcore: Efficient and Scalable Serverless Computing for Latency-Sensitive, Interactive Microservices
• [Paper Review]
  A Split Cache Hierarchy for Enabling Data-Oriented Optimizations
• [Paper Review]
  The Direct-to-Data (D2D) Cache: Navigating the Cache Hierarchy with a Single Lookup
• [Paper Review]
  Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy
• [Paper Review]
  A Case for Richer Cross-Layer Abstractions: Bridging the Semantics Gap with Expressive Memory
• [Paper Review]
  Stash: Have Your Scratchpad and Cache It Too
• [Paper Review]
  Typed Architectures: Architectural Support for Lightweight Scripting
• [Paper Review]
  ShortCut: Architectural Support for Fast Object Access in Scripting Languages
• [Paper Review]
  TLC: A Tag-Less Cache for Reducing Dynamic First Level Cache Energy
• [Paper Review]
  Fast Allocation and Deallocation of Memory Based on Object Lifetimes
• [Paper Review]
  An Object Oriented Architecture
• [Paper Review]
  Ribbon: High-Performance Cache Line Flush for Persistent Memory
• [Paper Review]
  Extending The Lifetime of NVMs with Compression
• [Paper Review]
  DPFC: A Dynamic Frequent Pattern Compression Scheme in NVM-Based Main Memory
• [Paper Review]
  Parallel Compression with Cooperative Dictionary Construction
• [Paper Review]
  Data Locality Exploitation in Cache Compression
• [Paper Review]
  Synergistic Cache Layout for Reuse and Compression
• [Paper Review]
  Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications
• [Paper Review]
  Rebooting Virtual Memory with Midgard
• [Paper Review]
  Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors
• [Paper Review]
  A Space-Efficient Compressed Cache Organization for High Performance Computing
• [Paper Review]
  Opportunistic Compression for Direct-Mapped DRAM Caches
• [Paper Review]
  Doppleganger: A Cache for Approximate Computing
• [Paper Review]
  Smaller and Faster: Parallel Processing of Compressed Graphs with Ligra++
• [Paper Review]
  SpZip: Architectural Support for Effective Data Compression in Irregular Applications
• [Paper Review]
  Crafty: Efficient, HTM-Compatible Persistent Transactions
• [Paper Review]
  Rethinking File Mapping for Persistent Memory
• [Paper Review]
  SPHT: Scalable Persistent Hardware Transactions
• [Paper Review]
  ArchTM: Architecture-Aware, High Performance Transaction for Persistent Memory
• [Paper Review]
  PMEM-Spec: Persistent Memory Speculation
• [Paper Review]
  Hippocrates: Healing Persistent Memory Bugs without Doing Any Harm
• [Paper Review]
  RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization
• [Paper Review]
  Clobber-NVM: Log Less, Re-execute More
• [Paper Review]
  BCD Deduplication: Effective Memory Compression Using Partial Cache-Line Deduplication
• [Paper Review]
  EXCITE-VM: Extending the Virtual Memory System to Support Snapshot Isolation Transactions
• [Paper Review]
  DeltaFS: Exascale File Systems Scale Better Without Dedicated Servers
• [Paper Review]
  Compaction-free Compressed Cache for High-Performance Multicore System
• [Paper Review]
  Better I/O Through Byte-Addressable, Persistent Memory
• [Paper Review]
  Lazy Release Persistency
• [Paper Review]
  Elastic Cuckoo Hashing Tables: Rethinking Virtual Memory Translation for Parallelism
• [Paper Review]
  Relaxed Persist Ordering Using Strand Persistency
• [Paper Review]
  Lelantus: Fine-Granularity Copy-On-Write Operations for Secure Non-Volatile Memories
• [Paper Review]
  HOOP: Efficient Hardware-Assisted Out-of-Place Update for Non-Volatile Memory
• [Paper Review]
  Buddy Compression: Enabling Large Memory for Deep Learning and HPC Workloads on GPU
• [Paper Review]
  InvisiFence: Performance-Transparent Memory Ordering in Conventional Multiprocessors
• [Paper Review]
  Boosting Store Buffer Efficiency with Store-Prefetch Bursts
• [Paper Review]
  Improving the Utilization of Micro-Operation Caches in x86 Processors
• [Paper Review]
  Speculative Enforcement of Store Atomicity
• [Paper Review]
  P-Inspect: Architectural Support for Programmable Non-Volatile Memory Frameworks
• [Paper Review]
  Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System
• [Paper Review]
  (Almost) Fence-Less Persistent Ordering
• [Paper Review]
  Data Compression Transformations for Dynamically Allocated Data Structures
• [Paper Review]
  Restrictive Compression Techniques to Increase Level 1 Cache Capacity
• [Paper Review]
  A Frequent-Value Based PRAM Memory Architecture
• [Paper Review]
  Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression
• [Paper Review]
  On-Line Memory Compression for Embedded Systems
• [Paper Review]
  LB+-Trees: Optimizing Persistent Index Performance on 3DXPoint Memory
• [Paper Review]
  Mostly Order Preserving Dictionaries
• [Paper Review]
  Super-Scalar RAM-CPU Cache Compression
• [Paper Review]
  Jenga: Software-Defined Cache Hierarchy
• [Paper Review]
  Gather-Scatter DRAM: In-DRAM Address Translation to Improve the Spatial Locality of Non-unit Strided Accesses
• [Paper Review]
  Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement
• [Paper Review]
  An Adaptive Memory Compression Scheme for Memory Traffic Minimization in Processor-Based Systems
• [Paper Review]
  Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures
• [Paper Review]
  Z-Rays: Divide Arrays and Conquer Speed and Flexibility
• [Paper Review]
  Distributed Shared Persistent Memory
• [Paper Review]
  AsymNVM: An efficient Framework for Implementing Persistent Data Structures on Asymmetric NVM Architecture
• [Paper Review]
  MOD: Minimally Ordered Durable Datastructures for Persistent Memory
• [Paper Review]
  Optimizing Hash-Array Mapped Tries for Fast and Lean Immutable JVM Collections
• [Paper Review]
  Pronto: Easy and Fast Persistence for Volatile Data Structures
• [Paper Review]
  Durable Transactional Memory Can Scale with TimeStone
• [Paper Review]
  Cooperative Cache Scrubbing
• [Paper Review]
  SoftWrAP: A Lightweight Framework for Transactional Support of Storage Class Memory
• Knowing Your Hardware ALU Shifter When Generating 64-bit Bit Masks
• [Paper Review]
  Automatically Characterizing Large Scale Program Behavior
• [Paper Review]
  A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps
• [Paper Review]
  A Case for Toggle-Aware Compression for GPU Systems
• [Paper Review]
  PageForge: A Near-Memory Content-Aware Page-Merging Architecture
• [Paper Review]
  FlatStore: An Efficient Los-Structured Key-Value Storage Engine for Persistent Memory
• [Paper Review]
  The Cache for Compressed Caching in Virtual Memory Systems
• [Paper Review]
  Thesaurus: Efficient Cache Compression via Dynamic Clustering
• [Paper Review]
  2DCC: Cache Compression in Two Dimensions
• [Paper Review]
  Lossless and Lossy Memory I/O Link Compression for Improving Performance of GPGPU Workloads
• [Paper Review]
  MemZip: Exploring Unconventional Benefits from Memory Compression
• [Paper Review]
  Dictionary Sharing: An Efficient Cache Compression Scheme for Compressed Caches
• [Paper Review]
  Yet Another Compressed Cache: A Los-Cost Yet Effective Compressed Cache
• [Paper Review]
  Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion
• [Paper Review]
  Transparent Dual Memory Compression Architecture
• [Paper Review]
  Compresso: Pragmatic Main Memory Compression
• [Paper Review]
  HyComp: A Hybrid Cache Compression Method for Selection of Data-Type-Specific Compression Methods
• [Paper Review]
  Compress Object, Not Cache Lines: An Object-Based Compressed Memory Hierarchy
• [Paper Review]
  Rethinking the Memory Hierarchy for Modern Languages
• [Paper Review]
  Frequent Value Locality and Value-Centric Data Cache Design
• [Paper Review]
  Design and Performance of a Main Memory Hardware Data Compressor
• [Paper Review]
  An on-chip cache compression technique to reduce decompression overhead and design complexity
• [Paper Review]
  A Unified Compressed Memory Hierarchy
• [Paper Review]
  Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines
• [Paper Review]
  Residual Cache: A Low-Energy Low-Area L2 Architecture via Compression andd Partial Hits
• [Paper Review]
  SC2: A Statistical Cache Compression Scheme
• [Paper Review]
  A Many-Core Oriented Compressed Cache
• [Paper Review]
  Zero-Value Cache: Cancelling Load That Returns Zero
• [Paper Review]
  Energy-Efficient Frequent Value Data Cache Design
• [Paper Review]
  Zero-Content Augmented Caches
• [Paper Review]
  Last-Level Cache Deduplication
• [Paper Review]
  System Software for Persistent Memory
• [Paper Review]
  Mojim: A Reliable and Highly Available Non-Volatile Memory System
• [Paper Review]
  Concurrent Support of Multiple Page Sizes On A Skewed Associative TLB
• [Paper Review]
  Skewed Compressed Caches
• [Paper Review]
  Decoupled Compressed Cache: Exploiting Spatial Locality for Energy-Optimized Compressed Caching
• [Paper Review]
  C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
• [Paper Review]
  Base-Victim Compression: A Opportunistic Cache Compression Architecture
• [Paper Review]
  MorLog: Morphable Hardware Logging for Atomic Persistence in Non-Volatile Main Memory
• [Paper Review]
  COP: To Compress and Protect Main Memory
• [Paper Review]
  Attache: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads
• [Paper Review]
  Touche: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overhead
• [Paper Review]
  Increasing TLB Reach Using Superpages Backed by Shadow Memory
• [Paper Review]
  Perforated Page: Supporting Fragmented Memory Allocation for Large Pages
• [Paper Review]
  Exploiting Compressed Block Size as an Indicator of Future Reuse
• [Paper Review]
  Pinnacle: IBM MXT in a Memory Controller Chip
• [Paper Review]
  A Robust Main-Memory Compression Scheme
• [Paper Review]
  Capturing Dynamic Memory Reference Bahavior with Adpative Cache Topology
• [Paper Review]
  Column Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches
• [Paper Review]
  Adaptive Line Placement with Set Balancing Cache
• [Paper Review]
  Scavenger: A New Last-Level Cache Architecture with Global Block Priority
• [Paper Review]
  The V-Way Cache: Demand Associativity via Global Replacement
• [Paper Review]
  The ZCache: Decoupling Ways and Associativity
• [Paper Review]
  Decoupled Sector Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio
• [Paper Review]
  A Fully-Associative Software-Managed Cache Design
• [Paper Review]
  Linear Compressed Pages: A Low Complexity, Low-Latency Main Memory Compression Framework
• [Paper Review]
  Adaptive Cache Compression for High-Performance Processors
• [Paper Review]
  Enabling Transparent Memory Compression on Commodity Memory
• [Paper Review]
  Pangolin: A Fault-Tolerant Persistent Memory Programming Library
• [Paper Review]
  Pisces: A Scalable and Efficient Persistent Transactional Memory
• [Paper Review]
  Romulus: Efficient Algorithms for Persistent Transactional Memory
• [Paper Review]
  Vilamb: Low Overhead Asynchronous Redundancy for Direct Access NVM
• [Paper Review]
  TVRAK: Software-Managed Hardware Offload for DAX NVM Storage Redundancy
• [Paper Review]
  SuperMem: Enabling Application-transparent Secure Persistent Memory with Low Overheads
• [Paper Review]
  Distributed Logless Atomic Durability with Persistent Memory
• [Paper Review]
  DHTM: Durable Hardware Transactional Memory
• [Paper Review]
  SSP: Eliminating Redundant Wrints in Failure-Atomic NVRAMs via Shadow Sub-Paging
• [Paper Review]
  Optimizing Systems for Byte-Addressable NVM by Reducing Bit Flipping
• [Paper Review]
  Write-Optimized Dynamic Hashing for Persistent Memory
• [Paper Review]
  Write-Optimized and High-Performance Hashing Index Scheme for Persistent Memory
• [Paper Review]
  NV-Tree: Reducing Consistency Cost for NVM-based Single Level Systems
• [Paper Review]
  WORT: Write Optimal Radix Tree for Persistent Memory Storage Systems
• [Paper Review]
  Asynchnized Concurrency: The Secret to Scaling Concurrent Search Data Structures
• [Paper Review]
  Quartz: A Lightweight Performance Emulator for Persistent Memory Software
• [Paper Review]
  Endurance Transient Inconsistency in Byte-Addressable Persistent B+Tree
• [Paper Review]
  SplitFS: Reducing Software Overhead in File Systems for Persistent Memory
• [Paper Review]
  Recipe: Converting Concurrent DRAM Indexes to Persistent-Memory Indexes
• [Paper Review]
  Makalu: Fast Recoverable Allocation of Non-Volatile Memory
• [Paper Review]
  FPTree: A Hybrid SCM-DRAM Persistent and Concurrent B-Tree for Storage Class Memory
• [Paper Review]
  Vorpal: Vector Clock Ordering for Large Persistent Memory Systems
• [Paper Review]
  An Empirical Guide to the Behavior and Use of Scalable Persistent Memory
• [Paper Review]
  Project PBerry: FPGA Acceleration for Remote Memory
• [Paper Review]
  BzTree: A High-Performance Latch-Free Range Index for Non-Volatile Memory
• [Paper Review]
  nvm_malloc: Memory Allocation for NVRAM
• [Paper Review]
  Easy Lock-Free Indexing in Non-Volatile Memory
• [Paper Review]
  A Practical Multi-Word Compare-And-Swap Operation
• [Paper Review]
  NVM Duet: Unified Working Memory and Persistent Store Architecture
• [Paper Review]
  An Efficient Software Transactional Memory Using Commit-Time Invalidation
• [Paper Review]
  Reduced Hardware NORec: A Safe and Scalable Hybrid TRansactional Memory
• [Paper Review]
  DEUCE: Write-Efficient Encryption for Non-Volatile Memories
• [Paper Review]
  CASPAR: Breaking Serialization in Lock-Free Multicore Synchronization
• [Paper Review]
  NVWAL: Exploiting NVRAM in Write-Ahead Logging
• [Paper Review]
  FlatFlash: Exploiting the Byte-Addressibility of SSDs within a Unified Memory-Storage Hierarchy
• [Paper Review]
  NOVA: A Log-Strictured File System for Hybrid Volatile/Non-volatile Main Memories
• [Paper Review]
  Failure-Atomic Slotted Paging for Persistent Memory
• [Paper Review]
  Finding and Fixing Performance Pathologies in Persistent Memory Software Stacks
• [Paper Review]
  Read-Log-Update
• [Paper Review]
  pLock: A Fast Lock for Architectures with Explicit Inter-Core Message Passing
• [Paper Review]
  Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory
• [Paper Review]
  PMTest: A Fast and Flexible Testing Framework for Persist Memory Programs
• [Paper Review]
  Fine-Grain Checkpointing With In-Cache-Line Logging
• [Paper Review]
  Hardware Transactional Memory for GPU Architectures
• [Paper Review]
  HeTM: Transactional Memory for Heterogeneous Systems
• [Paper Review]
  ForgiveTM: Supporting Lazy Conflict Detection on Eager Hardware Transactional Memory
• [Paper Review]
  Efficient Register Renaming and Recovery for High Performance Processors
• [Paper Review]
  Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
• [Paper Review]
  Out-of-Order Commit Processors
• [Paper Review]
  Supporting x86-64 Address Translation for 100s of GPU Lanes
• [Paper Review]
  Reducing the Cost of Persistence for Nonvolatile Heaps in End User Devices
• [Paper Review]
  Tag Tables
• [Paper Review]
  Fundamental Latency Trade-offs in Architecting DRAM Caches
• [Paper Review]
  Efficiently Enabling Conventional Block Sizes for Very Large Die-Stacked DRAM Caches
• [Paper Review]
  Dynamic Register Renaming Through Virtual-Physical Registers
• [Paper Review]
  Consistent and Durable Data Structures for Non-Volatile Byte-Addressable Memory
• [Paper Review]
  Atomic Persistence for SCM with a Non-Intrusive Backend Controller
• [Paper Review]
  A Novel Register Renaming Technique for Out-of-Order Processors
• [Paper Review]
  SpaceJMP: Programming with Multiple Virtual Address Spaces
• [Paper Review]
  Achieving Non-Inclusive Cache Performance with Inclusive Caches
• [Paper Review]
  Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects
• [Paper Review]
  Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB
• [Paper Review]
  CSALT: Context Switch Aware Large TLB
• [Paper Review]
  Improving the Performance and Ensurance of Encrypted Non-Volatile Main Memory through Deduplicated Writes
• [Paper Review]
  STRAIGHT: Hazardless Processor Architecture Without Register Renaming
• [Paper Review]
  A Scalable Architecture for Ordered Parallelism
• [Paper Review]
  iDO: Compiler-Directed Failure Atomicity for Non-Volatile Memory
• [Paper Review]
  Failure-Atomic Persistent Memory Updates via JUSTDO Logging
• [Paper Review]
  The Superfluous Load Queue
• [Paper Review]
  Filter Caching for Free: The Untapped Potential for Store Buffer
• [Paper Review]
  Atlas: Leveraging Locks for Non-Volatile Memory Consistency
• [Paper Review]
  NVthreads: Practical Persistence for Multi-threaded Applications
• [Paper Review]
  Crash Consistency in Encrypted Non-Volatile Main Memory Systems
• [Paper Review]
  Janus: optimizing memory and storage support for non-volatile memory systems
• [Paper Review]
  Efficient Persist Barriers for Multicores
• [Paper Review]
  Hardware Supported Persistent Object Address Translation
• [Paper Review]
  Efficient Support of Position Independence on Non-Volatile Memory
• [Paper Review]
  Proteus: A Flexible and Fast Software Supported Hardware Logging Approach for NVM
• [Paper Review]
  Fast Databases with Fast Durability and Recovery Through Multicore Parallelism
• [Paper Review]
  Speculative Memory Checkpointing
• [Paper Review]
  Survive: Pointer-Based In-DRAM Incremental Checkpointing for Low-Cost Data Persistence and Rollback-Recovery
• [Paper Review]
  ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
• [Paper Review]
  Dual-Page Checkpointing: An Architectural Approach to Efficient Data Persistence for In-Memory Applications
• [Paper Review]
  Log-Structured Memory for DRAM-based Storage
• [Paper Review]
  Log-Structured Non-Volatile Main Memory
• [Paper Review]
  Kiln: Closing the Performance Gap Between Systems With and Without Persistence Support
• [Paper Review]
  Hiding the Long Latency of Persist Barriers Using Speculative Execution
• [Paper Review]
  ATOM: Atomic Durability in Non-Volatile Memory through Hardware Logging
• [Paper Review]
  ThyNVM: Enabling Software-Transparent Crash Consistency in Persistent Memory Systems
• [Paper Review]
  PiCL: A Software Transparent, Persistent Cache Log for Nonvolatile Main Memory
• [Paper Review]
  Consistent, Durable, and Safe Memory Management for Byte-Addressable Non-Volatile Main Memory
• [Paper Review]
  Storage Management in the NVRAM Era
• [Paper Review]
  Scalable Logging Through Emerging Non-Volatile Memory
• [Paper Review]
  ARIES: Atransaction Recivery Method Supporting Fine-Granularity Locking and Partial Rollbacks Using Write-Ahead Logging
• [Paper Review]
  Delegated Persist Ordering
• [Paper Review]
  Efficient Hardware-assisted Logging with Asynchronous and Direct-Update for Persistent Memory
• [Paper Review]
  Steal but No Force: Efficient Hardware Undo+Redo Logging for Persistent Memory Systems
• [Paper Review]
  Write-Behind Logging
• [Paper Review]
  Lease/Release: Architectural Support for Scaling Contended Data Structures
• [Paper Review]
  DudeTM: Building Durable Transactions with Decoupling for Persistent Memory
• [Paper Review]
  Black-Box Concurrent Data Structures for NUMA Architectures
• [Paper Review]
  IMP: Indirect Memory Prefetcher
• [Paper Review]
  Translation-Triggered Prefetching
• [Paper Review]
  Mallacc: Accelerating Memory Allocation
• [Paper Review]
  Simple Rational Guidance for Chopping Up Transactions
• [Paper Review]
  Filtering Translation Bandwidth with Virtual Caching
• [Paper Review]
  Interval Based Memory Reclamation
• [Paper Review]
  LATR: Lazy Translation Coherence
• [Paper Review]
  Devirtualizing Memory in Heteogeneous System
• [Paper Review]
  UNified Instruction/Translation/Data (UNITD) Coherence: One Protocol to Rule Them All
• [Paper Review]
  Transactional Collection Classes
• [Paper Review]
  Multi-Version Concurrency via Timestamp Range Conflict Management
• [Paper Review]
  MaaT: Effective and Scalable Coordination of Distributed Transactions in the Cloud
• [Paper Review]
  EcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory
• [Paper Review]
  Transaction Monitors for Concurrent Objects
• [Paper Review]
  Predictive Log-Syncrhonization
• [Paper Review]
  What Really Makes Transaction Faster?
• [Paper Review]
  Fast Serializable Multi-Version Concurrency Control for Main-Memory Database Systems
• [Paper Review]
  Stretching Transactional Memory
• [Paper Review]
  A Comprehensive Strategy for Contention Management in Software Transactional Memory
• [Paper Review]
  STM in the Small: Trading Generality for Performance in Software Transactional Memory
• [Paper Review]
  Lightweight Locking for Main Memory Database Systems
• [Paper Review]
  Rethinking serializable multiversion concurrency control
• [Paper Review]
  Serializable Isolation for Snapshot Databases
• [Paper Review]
  BCC: Reducing False Aborts in Optimistic Concurrency Control with Low Cost for In-Memory Databases
• [Paper Review]
  Hardware Support for Relaxed Concurrency Support In Transactional Memory
• [Paper Review]
  OmniOrder: Directory-Based Conflict Serialization of Transactions
• [Paper Review]
  High Performance Cache Replacement Using Re-Reference Interval Prediction
• [Paper Review]
  Energy Efficient Address Translation
• [Paper Review]
  The V-Way Cache: Demand-Based Associativity via Global Replacement
• [Paper Review]
  Efficient Footprint Caching for Tagless DRAM Caches
• [Paper Review]
  A fully associative, tagless DRAM cache
• [Paper Review]
  Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures
• [Paper Review]
  Efficient virtual memory for big memory servers
• [Paper Review]
  Hardware Multithreaded Transactions
• [Paper Review]
  Maintaining Consistent Transactional States without a Global Clock
• [Paper Review]
  Reduced hardware transactions: a new approach to hybrid transactional memory
• [Paper Review]
  Hardware Extensions to Make Lazy Subscription Safe
• [Paper Review]
  Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
• [Paper Review]
  The Dirty-Block Index
• [Paper Review]
  Performance Improvement via Always-Abort HTM
• [Paper Review]
  Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
• [Paper Review]
  Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches
• [Paper Review]
  Redundant Memory Mappings for Fast Access to Large Memories
• [Paper Review]
  DICE: Compressing DRAM Caches for Bandwidth and Capacity
• [Paper Review]
  SIPT: Speculatively Indexed, Physically Tagged Caches
• [Paper Review]
  Agile Paging: Exceeding the Best of Nested and Shadow Paging
• [Paper Review]
  The Direct-to-Data (D2D) Cache: Navigating the Cache Hierarchy with a Single Lookup
• [Paper Review]
  Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB
• [Paper Review]
  A Lazy Snapshot Algorithm with Eager Validation
• [Paper Review]
  Experimental Evaluation of Real-Time Optimistic Concurrency Control Schemes
• [Paper Review]
  Using Dynamic Adjustment of Serialization Order for Real-Time Database Systems
• [Paper Review]
  Concurrent Certifications by Intervals of Timestamps in Distributed Database Systems
• [Paper Review]
  Concurrency Control in Database Systems: A Step Towards the Integration of Optimistic Methods and Locking
• [Paper Review]
  NOrec: Streamlining STM by Abolishing Ownership Records
• [Paper Review]
  Transactional Mutex Locks
• [Paper Review]
  RingSTM: Scalable Transactions with a Single Atomic Instruction
• Analyzing Optimistic Concurrency Control Anomalies and Solutions
• [Paper Review]
  Improving the Performance of an Optimistic Concurrency Control Algorithm Through Timestamps and Versions
• [Paper Review]
  Transactional Locking II
• [Paper Review]
  SI-TM: Reducing Transactional Memory Abort Rates Through Snapshot Isolation
• [Paper Review]
  Transactional Conflict Decoupling and Value Prediction
• Hardware Transactional Memory: Hardware Two Phase Locking and Optimistic Concurrency Control
• [Paper Review]
  An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees
• [Paper Review]
  EazyHTM: Eager-Lazy Hardware Transactional Memory

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