Top Posts
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Understanding Redis Source Code
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Cheat Sheet for Building and Deploying SPEC
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QEMU Cheat Sheet for Full-System Simulation
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Understanding Discrete Event Contention Simulation in zSim
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Understanding Cache Coherence Concurrency Control Protocol in zSim
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Understanding Processor Microarchitecture Simulation in zSim
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Understanding Cache System Simulation in zSim
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Adding Dynamic Github Contribution Calendar To Your Static Page
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SpecFaaS: Accelerating Serverless Applications with Speculative Function Execution
Keyword: Serverless; Speculative Execution; SpecFaaS -
Reducing DRAM Footprint with NVM in Facebook
Keyword: NVM; RockDB; NVM Cache -
Read-Log-Update: A Lightweight Synchronization Mechanism for Concurrent Programming
Keyword: RCU; RLU; STM; Read-Log-Update -
Delta pointers: buffer overflow checks without the checks
Keyword: Memory Safety; Delta Pointer; Pointer Tagging -
Cuckoo Trie: Exploiting Memory-Level Parallelism for Efficient DRAM Indexing
Keyword: B+Tree; Trie; Cuckoo Hashing; Cuckoo Trie -
Wormhole: A Fast Ordered Index for In-memory Data Management
Keyword: B+Tree; Trie; Hash Table; Wormhole -
Bridging the Performance Gap for Copy-based Garbage Collectors atop Non-Volatile Memory
Keyword: Java; Garbage Collection; NVM -
ResPCT: Fast Checkpointing in Non-volatile Memory for Multi-threaded Applications
Keyword: NVM; ResPCT; Undo Logging; Memory Snapshot; Epoch-Based Snapshot -
FaaSnap: FaaS made fast using snapshot-based VMs
Keyword: Serverless; Cold-Start Latency; Snapshotting; Virtual Machine; Firecracker -
In-fat pointer: hardware-assisted tagged-pointer spatial memory safety defense with subobject granularity protection
Keyword: Fat Pointer; Memory Safety -
PTEMagnet: fine-grained physical memory reservation for faster page walks in public clouds
Keyword: Virtualization; Page Table; Buddy Allocator; PTEMagnet -
CARAT CAKE: Replacing Paging via Compiler/Kernel Cooperation
Keyword: Carat; Compiler; TLB; OS -
MineSweeper: A Clean Sweep for Drop-In Use-after-Free Prevention
Keyword: malloc; security -
Libnvmmio: Reconstructing Software IO Path with Failure-Atomic Memory-Mapped Interface
Keyword: NVM; Libnvmmio; File System -
Austere Flash Caching with Deduplication and Compression
Keyword: SSD; Caching; Flash Caching -
FlatFS: Flatten Hierarchical File System Namespace on Non-volatile Memories
Keyword: NVM; FlatFS; File System -
FlatStore: An Efficient Log-Structured Key-Value Storage Engine for Persistent Memory
Keyword: NVM; FlatStore; Key-Value Store; Log-Structured -
Pacman: An Efficient Compaction Approach for Log-Structured Key-Value Store on Persistent Memory
Keyword: NVM; Pacman; Log-structured NVM; Key-Value Store; NVM -
Hardware-based Always-On Heap Memory Safety
Keyword: AOS; Allocator; malloc; Memory Safety -
ATTC (@C): Addressable-TLB based Translation Coherence
Keyword: ATTC; TLB Shootdown; Virtualization -
Enhancing Address Translations in Throughput Processors via Compression
Keyword: GPGPU; TLB Compression; Compression -
Memory Deduplication for Serverless Computing with Medes
Keyword: Serverless; Deduplication; Cold-Start Latency -
HTMFS: Strong Consistency Comes for Free with Hardware Transactional Memory in Persistent Memory File Systems
Keyword: NVM; File System; HTM -
Page Size Aware Cache Prefetching
Keyword: Prefetching; Set Dueling; Huge Page -
Translation-optimized Memory Compression for Capacity
Keyword: Memory Compression; TMCC; Deflate -
DaxVM: Stressing the Limits of Memory as a File Interface
Keyword: Virtual Memory; NVM; mmap -
Cocoa: Synergistic Cache Compression and Error Correction in Capacity Sensitive Last Level Caches
Keyword: Cache Compression; BDI; ECC -
Dual Dictionary Compression for the Last Level Cache
Keyword: Cache Compression; Dictionary Compression -
The reuse cache: downsizing the shared last-level cache
Keyword: Reuse Cache; RRIP; Decoupled Tag-Data -
Dynamic Dictionary-Based Data Compression for Level-1 Caches
Keyword: Cache Compression; L1 Compression; Frequent Value Compression; Dynamic Dictionary -
Frequent value compression in data caches
Keyword: Cache Compression; L1 Compression; Frequent Value Compression -
Cache Compression with Efficient in-SRAM Data Comparison
Keyword: LLC; Compression; In-SRAM Compression -
Making Huge Pages Actually Useful
Keyword: TLB; Huge Page; Virtual Memory; Illuminator; THP -
Trident: Harnessing Architectural Resources for All Page Sizes in x86 Processors
Keyword: TLB; Huge Page; Virtual Memory; Trident; THP -
Software-Defined Address Mapping: A Case on 3D Memory
Keyword: 3D Memory; HBM; HMC; DRAM; SDAM -
EveryWalk’s a Hit: Making PageWalks Single-Access Cache Hits
Keyword: TLB; Virtual Memory; Page Walk -
Free Atomics: Hardware Atomic Operations without Fences
Keyword: Load Queue; Store Queue; Atomics; Memory Consistency -
Lukewarm serverless functions: characterization and optimization
Keyword: Serverless; Prefetching; Jukebox; Function Keep-Alive; Instruction Cache -
ASAP: Architecture Support for Asynchronous Persistence
Keyword: NVM; ASAP; Asynchronous Commit; Undo Logging -
NvMR: Non-Volatile Memory Renaming for Intermittent Computing
Keyword: NVM; Intermittent Computing; NVMR; Idempotent Execution -
GBDI: Going Beyond Base-Delta-Immediate Compression with Global Bases
Keyword: Memory Compression; BDI; GBDI -
Exploiting Inter-block Entropy to Enhance the Compressibility of Blocks with Diverse Data
Keyword: Memory Compression; EPC; Pattern-Based Compression; Attache -
Understanding Memory Hierarchy Simulation in SST
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Understanding Ariel Core Simulation in SST
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Understanding Simulation Infrastructure in SST
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Understanding TLB Simulation in Samba (SST)
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Cerebros: Evading the RPC Tax in Datacenters
Keyword: RPC Tax; Accelerator; Cerebros -
COSPlay: Leveraging Task-Level Parallelism for High-Throughput Synchronous Persistence
Keyword: NVM; Persist Barrier; COSPlay -
Architectural Implications of Function-as-a-Service Computing
Keyword: Serverless; Benchmarking -
FaaSM: Lightweight Isolation for Efficient Stateful Serverless Computing
Keyword: Serverless; WebAssembly -
Benchmarking, Analysis, and Optimization of Serverless Function Snapshots
Keyword: Serverless; Keep-Alive; Caching Policy; REAP; Serverless Snapshot -
Serverless in the Wild: Characterizing and Optimizing the Serverless Workload at a Large Cloud Provider
Keyword: Serverless; Azure; Caching Policy -
Peeking Behind the Curtains of Serverless Platforms
Keyword: Serverless; AWS Lambda -
Serverless Computation with OpenLambda
Keyword: Serverless; OpenLambda -
FaaSCache: Keeping Serverless Computing Alive with Greedy-Dual Caching
Keyword: Serverless; FaaSCache; Caching Policy; Greedy-Dual Caching -
Cloudburst: Stateful Function-as-a-Service
Keyword: Serverless; CloudBurst; Key-Value Store -
Serverless Computing: One Step Forward, Two Steps Back
Keyword: Serverless; Lambda -
SAND: Towards High-Performance Serverless Computing
Keyword: Container; Serverless; SAND -
Scalable Architectural Support for Trusted Software
Keyword: Security; Enclave; Bastion -
Firecracker: Lightweight Virtualization for Serverless Applications
Keyword: Virtual Machine; Serverless; Lambda -
BabelFish: Fuse Address Translation for Containers
Keyword: Virtual Memory; Linux; Paging; MMU; Containers; BabelFish -
SOCK: Rapid Task Provisioning with Serverless-Optimized Containers
Keyword: Microservice; Serverless; OS; Process Template; SOCK -
Catalyzer: Sub-Millisecond Startup for Serverless Computing with Initialization-Less Booting
Keyword: Microservice; Serverless; OS; Process Template; Catalyzer -
SEUSS: Skip Redundant Paths to Make Serverless Fast
Keyword: Microservice; Serverless; OS; Process Template; SEUSS -
Put the "Micro" Back in Microservice
Keyword: Microservice; Serverless; OS -
Nightcore: Efficient and Scalable Serverless Computing for Latency-Sensitive, Interactive Microservices
Keyword: Nightcore; microservice; serverless -
A Split Cache Hierarchy for Enabling Data-Oriented Optimizations
Keyword: D2M Cache; TLB -
The Direct-to-Data (D2D) Cache: Navigating the Cache Hierarchy with a Single Lookup
Keyword: D2D Cache; TLB -
Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy
Keyword: Amoeba-Cache; Tag-less Cache -
A Case for Richer Cross-Layer Abstractions: Bridging the Semantics Gap with Expressive Memory
Keyword: Tagged Architecture; XMEM -
Stash: Have Your Scratchpad and Cache It Too
Keyword: Scratchpad memory; Stash; GPGPU -
Typed Architectures: Architectural Support for Lightweight Scripting
Keyword: Typed Architecture -
ShortCut: Architectural Support for Fast Object Access in Scripting Languages
Keyword: ShortCut; Virtual Function; BTB -
TLC: A Tag-Less Cache for Reducing Dynamic First Level Cache Energy
Keyword: Cache; TLB; TLC; Tag-Less Cache -
Fast Allocation and Deallocation of Memory Based on Object Lifetimes
Keyword: malloc -
An Object Oriented Architecture
Keyword: Object Oriented Architecture; COM -
Ribbon: High-Performance Cache Line Flush for Persistent Memory
Keyword: NVM; CLF; Ribbon -
Extending The Lifetime of NVMs with Compression
Keyword: NVM; FPC; Compression -
DPFC: A Dynamic Frequent Pattern Compression Scheme in NVM-Based Main Memory
Keyword: NVM; FPC; DFPC; Compression -
Parallel Compression with Cooperative Dictionary Construction
Keyword: LZ; LZSS; Parallel Compression -
Data Locality Exploitation in Cache Compression
Keyword: YACC; DISH; Dual-Block Compression -
Synergistic Cache Layout for Reuse and Compression
Keyword: YACC; Reuse Cache; FITFUB; First Use -
Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications
Keyword: Ripple; i-cache; Cache Replacement -
Rebooting Virtual Memory with Midgard
Keyword: Virtual Memory; Segmentation; Midgard -
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors
Keyword: Memory Compression; Delta Encoding; diff123 -
A Space-Efficient Compressed Cache Organization for High Performance Computing
Keyword: FCMS; Cache Compression; Memory Compression -
Opportunistic Compression for Direct-Mapped DRAM Caches
Keyword: DRAM Cache; Opportunistic Compression; Alloy Cache -
Doppleganger: A Cache for Approximate Computing
Keyword: Cache Compression; Deduplication; Doppleganger Cache -
Smaller and Faster: Parallel Processing of Compressed Graphs with Ligra++
Keyword: Compression; Graph Compression; Ligra+ -
SpZip: Architectural Support for Effective Data Compression in Irregular Applications
Keyword: SpZip; Compression; Data Flow Execution -
Crafty: Efficient, HTM-Compatible Persistent Transactions
Keyword: NVM; HTM; Crafty; TSX/RTM -
Rethinking File Mapping for Persistent Memory
Keyword: NVM; File System; Cuckoo Hashing -
SPHT: Scalable Persistent Hardware Transactions
Keyword: NVM; SPHT; HTM -
ArchTM: Architecture-Aware, High Performance Transaction for Persistent Memory
Keyword: NVM; STM; ArchTM -
PMEM-Spec: Persistent Memory Speculation
Keyword: NVM; PMEM-Spec; Speculation -
Hippocrates: Healing Persistent Memory Bugs without Doing Any Harm
Keyword: NVM; Bug Finding; Hippocrates -
RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization
Keyword: RowClone; DRAM -
Clobber-NVM: Log Less, Re-execute More
Keyword: NVM; Clobber Logging; iDO; JUSTDO; Semantics Logging; Resumption -
BCD Deduplication: Effective Memory Compression Using Partial Cache-Line Deduplication
Keyword: Compression; Memory Compression; Deduplication; Inter-Block Compression -
EXCITE-VM: Extending the Virtual Memory System to Support Snapshot Isolation Transactions
Keyword: Virtual Memory; STM; SI-TM; EXCITE-VM -
DeltaFS: Exascale File Systems Scale Better Without Dedicated Servers
Keyword: File System; DeltaFS -
Compaction-free Compressed Cache for High-Performance Multicore System
Keyword: Cache Compression -
Better I/O Through Byte-Addressable, Persistent Memory
Keyword: NVM; BPFS; File System -
Lazy Release Persistency
Keyword: NVM; Persistency Model; LRP; Release Persistency -
Elastic Cuckoo Hashing Tables: Rethinking Virtual Memory Translation for Parallelism
Keyword: Virtual Memory; Page Table; Cuckoo Hashing -
Relaxed Persist Ordering Using Strand Persistency
Keyword: NVM; Write Ordering; Strand Persistency; StrandWeaver -
Lelantus: Fine-Granularity Copy-On-Write Operations for Secure Non-Volatile Memories
Keyword: NVM; CoW; Virtual Memory -
HOOP: Efficient Hardware-Assisted Out-of-Place Update for Non-Volatile Memory
Keyword: NVM; Redo Logging; HOOP -
Buddy Compression: Enabling Large Memory for Deep Learning and HPC Workloads on GPU
Keyword: Compression; GPU Compression Buddy Compression -
InvisiFence: Performance-Transparent Memory Ordering in Conventional Multiprocessors
Keyword: Microarchitecture; Store Buffer; Memory Consistency -
Boosting Store Buffer Efficiency with Store-Prefetch Bursts
Keyword: Microarchitecture; Store Buffer -
Improving the Utilization of Micro-Operation Caches in x86 Processors
Keyword: Microarchitecture; uop cache -
Speculative Enforcement of Store Atomicity
Keyword: Microarchitecture; LSQ; Pipeline; Store Atomicity -
P-Inspect: Architectural Support for Programmable Non-Volatile Memory Frameworks
Keyword: NVM; P-Inspect -
Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System
Keyword: NVM; HTM; UHTM -
(Almost) Fence-Less Persistent Ordering
Keyword: NVM; Persistent Barrier; Themis -
Data Compression Transformations for Dynamically Allocated Data Structures
Keyword: Compression; -
Restrictive Compression Techniques to Increase Level 1 Cache Capacity
Keyword: Compression; L1 Compression -
A Frequent-Value Based PRAM Memory Architecture
Keyword: Compression; NVM; Frequent Value Compression -
Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression
Keyword: Compression; NVM; DRAM Cache -
On-Line Memory Compression for Embedded Systems
Keyword: Compression; DRAM Compression; CREAMES; Embedded compression -
LB+-Trees: Optimizing Persistent Index Performance on 3DXPoint Memory
Keyword: NVM; B+Tree; LB-Tree -
Mostly Order Preserving Dictionaries
Keyword: Compression; Database Compression; MOP; Order-Preserving Dictionary -
Super-Scalar RAM-CPU Cache Compression
Keyword: Compression; Database Compression -
Jenga: Software-Defined Cache Hierarchy
Keyword: Cache; Jenga; Software-Defined Cache -
Gather-Scatter DRAM: In-DRAM Address Translation to Improve the Spatial Locality of Non-unit Strided Accesses
Keyword: DRAM; GS-DRAM; -
Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement
Keyword: Micro Pages; Virtual Memory; DRAM -
An Adaptive Memory Compression Scheme for Memory Traffic Minimization in Processor-Based Systems
Keyword: Compression; Adaptive Compression; Dictionary Encoding -
Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures
Keyword: Bit-Plane Compression; Compression; GPGPU -
Z-Rays: Divide Arrays and Conquer Speed and Flexibility
Keyword: Array; ZRay; Data Structure -
Distributed Shared Persistent Memory
Keyword: NVM; Redo Logging; Shadow Paging; Hotpot -
AsymNVM: An efficient Framework for Implementing Persistent Data Structures on Asymmetric NVM Architecture
Keyword: NVM; Redo Logging; Semantic Logging; AsymNVM -
MOD: Minimally Ordered Durable Datastructures for Persistent Memory
Keyword: NVM; MOD; Data Structure; Shadow Paging -
Optimizing Hash-Array Mapped Tries for Fast and Lean Immutable JVM Collections
Keyword: HAMP; CHAMP; Persistent Data Structure -
Pronto: Easy and Fast Persistence for Volatile Data Structures
Keyword: NVM; Pronto; Logical Logging -
Durable Transactional Memory Can Scale with TimeStone
Keyword: NVM; MVCC; STM; TimeStone; Redo Logging -
Cooperative Cache Scrubbing
Keyword: Cache; Cache Scrubbing -
SoftWrAP: A Lightweight Framework for Transactional Support of Storage Class Memory
Keyword: NVM; SoftWrap; Redo Logging -
Knowing Your Hardware ALU Shifter When Generating 64-bit Bit Masks
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Automatically Characterizing Large Scale Program Behavior
Keyword: Debugging; SimPoints -
A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps
Keyword: Compression; GPU; BDI; CABA -
A Case for Toggle-Aware Compression for GPU Systems
Keyword: Compression; GPU; Link Compression -
PageForge: A Near-Memory Content-Aware Page-Merging Architecture
Keyword: Page Deduplication; PageForge -
FlatStore: An Efficient Los-Structured Key-Value Storage Engine for Persistent Memory
Keyword: NVM; FlatStore; Log-structured -
The Cache for Compressed Caching in Virtual Memory Systems
Keyword: Compression; Memory Compression; WK Compression -
Thesaurus: Efficient Cache Compression via Dynamic Clustering
Keyword: Compression; Cache Compression; Fingerprint hash; 2D compression; Thesaurus -
2DCC: Cache Compression in Two Dimensions
Keyword: Compression; Cache Compression; 2DCC; Deduplication; 2d Compression -
Lossless and Lossy Memory I/O Link Compression for Improving Performance of GPGPU Workloads
Keyword: Compression; Memory Compression; GPGPU; Floating Number Compression -
MemZip: Exploring Unconventional Benefits from Memory Compression
Keyword: Compression; Memory Compression; Subranking; Memzip -
Dictionary Sharing: An Efficient Cache Compression Scheme for Compressed Caches
Keyword: Compression; Cache Compression; DISH -
Yet Another Compressed Cache: A Los-Cost Yet Effective Compressed Cache
Keyword: Compression; Cache Compression; YACC -
Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion
Keyword: Compression; Memory Compression; Buri -
Transparent Dual Memory Compression Architecture
Keyword: Compression; Memory Compression; DCM; Dual Memory Compression -
Compresso: Pragmatic Main Memory Compression
Keyword: Compression; Memory Compression; Compresso -
HyComp: A Hybrid Cache Compression Method for Selection of Data-Type-Specific Compression Methods
Keyword: Cache; Compression; HyComp; Hybrid Compression; Floating Point Number Compression -
Compress Object, Not Cache Lines: An Object-Based Compressed Memory Hierarchy
Keyword: Cache; Compression; Object; Hotpads; Zippads; COCO -
Rethinking the Memory Hierarchy for Modern Languages
Keyword: Cache; Hotpads -
Frequent Value Locality and Value-Centric Data Cache Design
Keyword: Compression; FVC; Frequent Value -
Design and Performance of a Main Memory Hardware Data Compressor
Keyword: Compression; X-Match; X-RL -
An on-chip cache compression technique to reduce decompression overhead and design complexity
Keyword: Cache; SCMS; Cache Compression -
A Unified Compressed Memory Hierarchy
Keyword: Cache; Cache Compression; ICC; ICC-C -
Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines
Keyword: Cache; LDIS; Line Distillation -
Residual Cache: A Low-Energy Low-Area L2 Architecture via Compression andd Partial Hits
Keyword: Cache; Compression; Residual Cache -
SC2: A Statistical Cache Compression Scheme
Keyword: Cache; Compression; Huffman Encoding -
A Many-Core Oriented Compressed Cache
Keyword: Cache; Compression; Log-structured Cache -
Zero-Value Cache: Cancelling Load That Returns Zero
Keyword: Cache; Compression; ZVC; Zero Compression -
Energy-Efficient Frequent Value Data Cache Design
Keyword: Cache; Compression; FVC -
Zero-Content Augmented Caches
Keyword: Cache; ZCA; Zero Compression -
Last-Level Cache Deduplication
Keyword: Cache; LLC; Deduplication -
System Software for Persistent Memory
Keyword: NVM; PMFS -
Mojim: A Reliable and Highly Available Non-Volatile Memory System
Keyword: NVM; Mojim; Replication -
Concurrent Support of Multiple Page Sizes On A Skewed Associative TLB
Keyword: Skewed TLB; TLB -
Skewed Compressed Caches
Keyword: Compression; Cache Tags; Skewed Cache -
Decoupled Compressed Cache: Exploiting Spatial Locality for Energy-Optimized Compressed Caching
Keyword: Compression; Cache Tags; DCC -
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Keyword: Compression; Cache Tags; C-Pack -
Base-Victim Compression: A Opportunistic Cache Compression Architecture
Keyword: Compression; Cache Tags; Base-Victim -
MorLog: Morphable Hardware Logging for Atomic Persistence in Non-Volatile Main Memory
Keyword: Logging; Undo Log; Redo Log; MorLog -
COP: To Compress and Protect Main Memory
Keyword: COP; Memory Compression; ECC -
Attache: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads
Keyword: Attache; Memory Compression -
Touche: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overhead
Keyword: Touche; Cache Compression; Cache Tag -
Increasing TLB Reach Using Superpages Backed by Shadow Memory
Keyword: Virtual Memory; Shadow Memory; Huge Page -
Perforated Page: Supporting Fragmented Memory Allocation for Large Pages
Keyword: Virtual Memory; Perforated Page -
Exploiting Compressed Block Size as an Indicator of Future Reuse
Keyword: CAMP; Cache; Compression -
Pinnacle: IBM MXT in a Memory Controller Chip
Keyword: Compression; MXT; Pinnacle -
A Robust Main-Memory Compression Scheme
Keyword: Compression; Paging -
Capturing Dynamic Memory Reference Bahavior with Adpative Cache Topology
Keyword: Cache; Group Associative -
Column Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches
Keyword: Cache; Column Associative -
Adaptive Line Placement with Set Balancing Cache
Keyword: Cache; SBC; Set Balancing -
Scavenger: A New Last-Level Cache Architecture with Global Block Priority
Keyword: Scavenger; Priority Queue; Heap -
The V-Way Cache: Demand Associativity via Global Replacement
Keyword: v-way cache -
The ZCache: Decoupling Ways and Associativity
Keyword: zCache -
Decoupled Sector Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio
Keyword: Sector Cache -
A Fully-Associative Software-Managed Cache Design
Keyword: Cache; IIC; Indirect Indexed Cache -
Linear Compressed Pages: A Low Complexity, Low-Latency Main Memory Compression Framework
Keyword: Memory Compression; LCP -
Adaptive Cache Compression for High-Performance Processors
Keyword: Cache Compression -
Enabling Transparent Memory Compression on Commodity Memory
Keyword: Memory Compression -
Pangolin: A Fault-Tolerant Persistent Memory Programming Library
Keyword: NVM; Pangolin; Redo Logging -
Pisces: A Scalable and Efficient Persistent Transactional Memory
Keyword: NVM; Transaction; Pisces -
Romulus: Efficient Algorithms for Persistent Transactional Memory
Keyword: NVM; Transaction; Romulus -
Vilamb: Low Overhead Asynchronous Redundancy for Direct Access NVM
Keyword: NVM; Vilamb; Checksum; Redundancy -
TVRAK: Software-Managed Hardware Offload for DAX NVM Storage Redundancy
Keyword: NVM; Tvrak; Checksum; Redundancy -
SuperMem: Enabling Application-transparent Secure Persistent Memory with Low Overheads
Keyword: NVM; SuperMem; Counter Mode Encryption -
Distributed Logless Atomic Durability with Persistent Memory
Keyword: NVM; LAD; Memory Controller -
DHTM: Durable Hardware Transactional Memory
Keyword: NVM; HTM; DHTM; Redo Logging -
SSP: Eliminating Redundant Wrints in Failure-Atomic NVRAMs via Shadow Sub-Paging
Keyword: NVM; SSP; Shadow Mapping; Double Buffering -
Optimizing Systems for Byte-Addressable NVM by Reducing Bit Flipping
Keyword: NVM; Bit Flip -
Write-Optimized Dynamic Hashing for Persistent Memory
Keyword: NVM; Hash Table; CCEH; Extendible Hashing -
Write-Optimized and High-Performance Hashing Index Scheme for Persistent Memory
Keyword: NVM; Hash Table; Level Hashing -
NV-Tree: Reducing Consistency Cost for NVM-based Single Level Systems
Keyword: NV-Tree; NVM; B+Tree -
WORT: Write Optimal Radix Tree for Persistent Memory Storage Systems
Keyword: ART; Radix Tree; WORT -
Asynchnized Concurrency: The Secret to Scaling Concurrent Search Data Structures
Keyword: Concurrency; Hash Table; ASCY -
Quartz: A Lightweight Performance Emulator for Persistent Memory Software
Keyword: NVM; Simulator -
Endurance Transient Inconsistency in Byte-Addressable Persistent B+Tree
Keyword: NVM; B+Tree; FAST; FAIR -
SplitFS: Reducing Software Overhead in File Systems for Persistent Memory
Keyword: NVM; File System; SplitFS -
Recipe: Converting Concurrent DRAM Indexes to Persistent-Memory Indexes
Keyword: NVM; B+Tree -
Makalu: Fast Recoverable Allocation of Non-Volatile Memory
Keyword: NVM; malloc; Makalu; Memory management -
FPTree: A Hybrid SCM-DRAM Persistent and Concurrent B-Tree for Storage Class Memory
Keyword: NVM; B+Tree -
Vorpal: Vector Clock Ordering for Large Persistent Memory Systems
Keyword: NVM; Vorpal; Vector clock; FASE -
An Empirical Guide to the Behavior and Use of Scalable Persistent Memory
Keyword: NVM -
Project PBerry: FPGA Acceleration for Remote Memory
Keyword: FPGA; Remote Memory -
BzTree: A High-Performance Latch-Free Range Index for Non-Volatile Memory
Keyword: MWCAS; NVM; BzTree -
nvm_malloc: Memory Allocation for NVRAM
Keyword: malloc; NVM -
Easy Lock-Free Indexing in Non-Volatile Memory
Keyword: MWCAS; NVM -
A Practical Multi-Word Compare-And-Swap Operation
Keyword: MWCAS -
NVM Duet: Unified Working Memory and Persistent Store Architecture
Keyword: NVM; NVM Duet -
An Efficient Software Transactional Memory Using Commit-Time Invalidation
Keyword: STM; InvalSTM; FOCC -
Reduced Hardware NORec: A Safe and Scalable Hybrid TRansactional Memory
Keyword: HTM; STM; NORec; Hybrid TM -
DEUCE: Write-Efficient Encryption for Non-Volatile Memories
Keyword: NVM; Counter Mode Encryption; DEUCE -
CASPAR: Breaking Serialization in Lock-Free Multicore Synchronization
Keyword: CAS; Cache Coherence; CASPAR; Synchronization; Lock-Free -
NVWAL: Exploiting NVRAM in Write-Ahead Logging
Keyword: NVM; WAL; SQLite; NVWAL; Database -
FlatFlash: Exploiting the Byte-Addressibility of SSDs within a Unified Memory-Storage Hierarchy
Keyword: SSD; Virtual Memory; FlatFlash -
NOVA: A Log-Strictured File System for Hybrid Volatile/Non-volatile Main Memories
Keyword: NVM; File System; NOVA; Log-Structured -
Failure-Atomic Slotted Paging for Persistent Memory
Keyword: NVM; FASH; FAST; B+Tree -
Finding and Fixing Performance Pathologies in Persistent Memory Software Stacks
Keyword: NVM; File System -
Read-Log-Update
Keyword: RLU; RCU; Synchronization -
pLock: A Fast Lock for Architectures with Explicit Inter-Core Message Passing
Keyword: SW26010; Synchronization; Lock; Message Passing -
Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory
Keyword: BTM; UFO; Hybrid TM; HTM; STM -
PMTest: A Fast and Flexible Testing Framework for Persist Memory Programs
Keyword: NVM, Undo Logging; Testing; PMTest -
Fine-Grain Checkpointing With In-Cache-Line Logging
Keyword: NVM, Undo Logging; Masstree -
Hardware Transactional Memory for GPU Architectures
Keyword: HTM; GPU; KiloTM -
HeTM: Transactional Memory for Heterogeneous Systems
Keyword: HTM; GPU -
ForgiveTM: Supporting Lazy Conflict Detection on Eager Hardware Transactional Memory
Keyword: HTM; Conflict Detection -
Efficient Register Renaming and Recovery for High Performance Processors
Keyword: ROB; Microarchitecture; Register Renaming -
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Keyword: ROB; Microarchitecture; Register Renaming -
Out-of-Order Commit Processors
Keyword: ROB; Microarchitecture -
Supporting x86-64 Address Translation for 100s of GPU Lanes
Keyword: GPU; Paging; TLB; Virtual Memory -
Reducing the Cost of Persistence for Nonvolatile Heaps in End User Devices
Keyword: NVM; Page Coloring; Logging -
Tag Tables
Keyword: L4 Cache; DRAM Cache; Tag Table; Page Table -
Fundamental Latency Trade-offs in Architecting DRAM Caches
Keyword: L4 Cache; DRAM Cache; Alloy Cache -
Efficiently Enabling Conventional Block Sizes for Very Large Die-Stacked DRAM Caches
Keyword: L4 Cache; DRAM Cache; LH Cache -
Dynamic Register Renaming Through Virtual-Physical Registers
Keyword: Register Renaming; Microarchitecture -
Consistent and Durable Data Structures for Non-Volatile Byte-Addressable Memory
Keyword: B+Tree; NVM; Versioning -
Atomic Persistence for SCM with a Non-Intrusive Backend Controller
Keyword: Logging; NVM; Memory Controller -
A Novel Register Renaming Technique for Out-of-Order Processors
Keyword: Register Renaming; Microarchitecture -
SpaceJMP: Programming with Multiple Virtual Address Spaces
Keyword: Virtual Memory -
Achieving Non-Inclusive Cache Performance with Inclusive Caches
Keyword: Inclusive Cache; Non-Inclusive Cache; Temporal Locality -
Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects
Keyword: TLB; NOCStar; NOC -
Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB
Keyword: TLB; POM-TLB; -
CSALT: Context Switch Aware Large TLB
Keyword: TLB; LRU; Cache Replacement -
Improving the Performance and Ensurance of Encrypted Non-Volatile Main Memory through Deduplicated Writes
Keyword: NVM; Counter Mode Encryption; Deduplication -
STRAIGHT: Hazardless Processor Architecture Without Register Renaming
Keyword: Register renaming; Straight; Microarchitecture -
A Scalable Architecture for Ordered Parallelism
Keyword: Swarm; TLS; HTM; Speculation -
iDO: Compiler-Directed Failure Atomicity for Non-Volatile Memory
Keyword: JUSTDO; iDO; Failure Atomicity; Idempotent Region -
Failure-Atomic Persistent Memory Updates via JUSTDO Logging
Keyword: Logging; JUSTDO; NVM -
The Superfluous Load Queue
Keyword: Load Queue; Speculative Execution; TSO -
Filter Caching for Free: The Untapped Potential for Store Buffer
Keyword: Store Buffer; Filter Cache -
Atlas: Leveraging Locks for Non-Volatile Memory Consistency
Keyword: NVM; Critical Section; Undo Logging -
NVthreads: Practical Persistence for Multi-threaded Applications
Keyword: NVM; Critical Section; Redo Logging -
Crash Consistency in Encrypted Non-Volatile Main Memory Systems
Keyword: NVM; Encryption; Counter Atomicity -
Janus: optimizing memory and storage support for non-volatile memory systems
Keyword: NVM; Encryption; Backend Memory Operation (BMO) -
Efficient Persist Barriers for Multicores
Keyword: NVM; persist barrier; persistency model -
Hardware Supported Persistent Object Address Translation
Keyword: NVM; mmap; Virtual Memory -
Efficient Support of Position Independence on Non-Volatile Memory
Keyword: NVM; mmap; Virtual Memory -
Proteus: A Flexible and Fast Software Supported Hardware Logging Approach for NVM
Keyword: NVM; Logging; Proteus -
Fast Databases with Fast Durability and Recovery Through Multicore Parallelism
Keyword: Database Recovery; Logging; Multicore -
Speculative Memory Checkpointing
Keyword: Checkpointing -
Survive: Pointer-Based In-DRAM Incremental Checkpointing for Low-Cost Data Persistence and Rollback-Recovery
Keyword: Checkpointing; NVM -
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
Keyword: Checkpointing -
Dual-Page Checkpointing: An Architectural Approach to Efficient Data Persistence for In-Memory Applications
Keyword: NVM; Durability; Checkpointing; Copy-on-Write -
Log-Structured Memory for DRAM-based Storage
Keyword: Log-Structured; NVM; Durability -
Log-Structured Non-Volatile Main Memory
Keyword: Log-Structured; NVM; Durability -
Kiln: Closing the Performance Gap Between Systems With and Without Persistence Support
Keyword: Kiln; NVM; Cache; LLC -
Hiding the Long Latency of Persist Barriers Using Speculative Execution
Keyword: NVM; Persist Barrier; Speculative Execution -
ATOM: Atomic Durability in Non-Volatile Memory through Hardware Logging
Keyword: NVM; Undo; ATOM -
ThyNVM: Enabling Software-Transparent Crash Consistency in Persistent Memory Systems
Keyword: NVM; Redo; Epoch; Checkpointing -
PiCL: A Software Transparent, Persistent Cache Log for Nonvolatile Main Memory
Keyword: NVM; Undo; Logging; PiCL; Checkpoint -
Consistent, Durable, and Safe Memory Management for Byte-Addressable Non-Volatile Main Memory
Keyword: NVM; Malloc; B+Tree -
Storage Management in the NVRAM Era
Keyword: ARIES; Recovery; Logging; NVM; Group Commit -
Scalable Logging Through Emerging Non-Volatile Memory
Keyword: ARIES; Recovery; Logging; NVM -
ARIES: Atransaction Recivery Method Supporting Fine-Granularity Locking and Partial Rollbacks Using Write-Ahead Logging
Keyword: ARIES; Recovery; Logging -
Delegated Persist Ordering
Keyword: Undo Logging; Persistence Ordering; NVM -
Efficient Hardware-assisted Logging with Asynchronous and Direct-Update for Persistent Memory
Keyword: Redo Logging; Durability; NVM; Redu -
Steal but No Force: Efficient Hardware Undo+Redo Logging for Persistent Memory Systems
Keyword: Logging; Durability; NVM -
Write-Behind Logging
Keyword: Logging; Durability; Transaction Processing; Database -
Lease/Release: Architectural Support for Scaling Contended Data Structures
Keyword: Cache Coherence; Concurrent Data Structure; Locking; Lock-free -
DudeTM: Building Durable Transactions with Decoupling for Persistent Memory
Keyword: NVM; HTM; Transaction -
Black-Box Concurrent Data Structures for NUMA Architectures
Keyword: NUMA; Concurrent Data Structure -
IMP: Indirect Memory Prefetcher
Keyword: Cache; Prefetching -
Translation-Triggered Prefetching
Keyword: TLB; Prefetching; DRAM -
Mallacc: Accelerating Memory Allocation
Keyword: malloc; Accelerator; Special Purpose Hardware -
Simple Rational Guidance for Chopping Up Transactions
Keyword: Transaction Chopping; Relaxed Concurrency Control -
Filtering Translation Bandwidth with Virtual Caching
Keyword: Virtual Cache; TLB; GPU; Accelerator -
Interval Based Memory Reclamation
Keyword: TLB Shootdown -
LATR: Lazy Translation Coherence
Keyword: TLB Shootdown -
Devirtualizing Memory in Heteogeneous System
Keyword: TLB; Virtual Memory; Accelerator; GPU -
UNified Instruction/Translation/Data (UNITD) Coherence: One Protocol to Rule Them All
Keyword: TLB; Coherence; TLB Shootdown -
Transactional Collection Classes
Keyword: Concurrency Control; MVCC; OCC; Interval-Based CC -
Multi-Version Concurrency via Timestamp Range Conflict Management
Keyword: Concurrency Control; MVCC; OCC; Interval-Based CC -
MaaT: Effective and Scalable Coordination of Distributed Transactions in the Cloud
Keyword: MaaT; Concurrency Control; OCC; Interval-Based CC -
EcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory
Keyword: EcoTM; HTM; Directory -
Transaction Monitors for Concurrent Objects
Keyword: OCC; STM; Monitor -
Predictive Log-Syncrhonization
Keyword: Log-Structured; STM; Lock-Free -
What Really Makes Transaction Faster?
Keyword: TL; STM -
Fast Serializable Multi-Version Concurrency Control for Main-Memory Database Systems
Keyword: MVCC; Hyper -
Stretching Transactional Memory
Keyword: STM; SwissTM; TL2 -
A Comprehensive Strategy for Contention Management in Software Transactional Memory
Keyword: STM; TL2; Contention Management -
STM in the Small: Trading Generality for Performance in Software Transactional Memory
Keyword: SpecTM; STM -
Lightweight Locking for Main Memory Database Systems
Keyword: Very Lighweight Locking; VLL -
Rethinking serializable multiversion concurrency control
Keyword: MVCC; Serializable; BOHM -
Serializable Isolation for Snapshot Databases
Keyword: MVCC; SSI; Snapshot Isolation -
BCC: Reducing False Aborts in Optimistic Concurrency Control with Low Cost for In-Memory Databases
Keyword: BCC; OCC -
Hardware Support for Relaxed Concurrency Support In Transactional Memory
Keyword: HTM; SONTM -
OmniOrder: Directory-Based Conflict Serialization of Transactions
Keyword: HTM; OmniOrder; Sequential Consistency -
High Performance Cache Replacement Using Re-Reference Interval Prediction
Keyword: RRIP; Cache Replacement; LRU -
Energy Efficient Address Translation
Keyword: TLB; Redundant Memory Mapping; Segmentation; RMM; Lite -
The V-Way Cache: Demand-Based Associativity via Global Replacement
Keyword: LLC; V-Way Cache; Global Replacement -
Efficient Footprint Caching for Tagless DRAM Caches
Keyword: cTLB; DRAM cache; tagless; footprint caching; over-fetching -
A fully associative, tagless DRAM cache
Keyword: cTLB; DRAM cache; tagless; TDC -
Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures
Keyword: BPC; Compression; Bit Plane -
Efficient virtual memory for big memory servers
Keyword: Direct Segment; Segmentation -
Hardware Multithreaded Transactions
Keyword: Thread Level Speculation; MOESI; Coherence; HMTX -
Maintaining Consistent Transactional States without a Global Clock
Keyword: TL2; STM; Global Clock; Thread Local Counter -
Reduced hardware transactions: a new approach to hybrid transactional memory
Keyword: Reduced HTM; Hybrid TM; TL2; RH1; RH2 -
Hardware Extensions to Make Lazy Subscription Safe
Keyword: Hybrid TM -
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Keyword: NORec; STM; Hybrid TM -
The Dirty-Block Index
Keyword: Dirty Block Index; Cache; Write Back -
Performance Improvement via Always-Abort HTM
Keyword: HTM; Thread-Level Speculation -
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
Keyword: Coherence; Scratchpad Memory -
Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches
Keyword: Cache Compression; Delta Encoding -
Redundant Memory Mappings for Fast Access to Large Memories
Keyword: Paging; Virtual Memory; Segmentation; RMM; -
DICE: Compressing DRAM Caches for Bandwidth and Capacity
Keyword: DRAM Cache; Cache Compression -
SIPT: Speculatively Indexed, Physically Tagged Caches
Keyword: Cache Hierarchy; Speculative Index -
Agile Paging: Exceeding the Best of Nested and Shadow Paging
Keyword: Agile Paging; Nested Paging; Shadow Page Table -
The Direct-to-Data (D2D) Cache: Navigating the Cache Hierarchy with a Single Lookup
Keyword: D2D Cache; TLB -
Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB
Keyword: POM-TLB -
A Lazy Snapshot Algorithm with Eager Validation
Keyword: LSA-STM; -
Experimental Evaluation of Real-Time Optimistic Concurrency Control Schemes
Keyword: FOCC -
Using Dynamic Adjustment of Serialization Order for Real-Time Database Systems
Keyword: FOCC; TIOCC -
Concurrent Certifications by Intervals of Timestamps in Distributed Database Systems
Keyword: OCC; FOCC; Dynamic Timestamp Allocation -
Concurrency Control in Database Systems: A Step Towards the Integration of Optimistic Methods and Locking
Keyword: OCC; 2PL; Hybrid -
NOrec: Streamlining STM by Abolishing Ownership Records
Keyword: NOrec; STM; OCC -
Transactional Mutex Locks
Keyword: STM; TML; Hybrid 2PL-OCC; ORec -
RingSTM: Scalable Transactions with a Single Atomic Instruction
Keyword: RingSTM -
Analyzing Optimistic Concurrency Control Anomalies and Solutions
-
Improving the Performance of an Optimistic Concurrency Control Algorithm Through Timestamps and Versions
Keyword: BOCC; Version validation -
Transactional Locking II
Keyword: TL2; commit-time lock acquisition; 2PL -
SI-TM: Reducing Transactional Memory Abort Rates Through Snapshot Isolation
Keyword: SI-TM; Snapshot Isolation; Multiversion CC -
Transactional Conflict Decoupling and Value Prediction
Keyword: DPTM (Decoupling and Prediction TM); Value Prediction; Validation -
Hardware Transactional Memory: Hardware Two Phase Locking and Optimistic Concurrency Control
-
An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees
Keyword: SigTM; Hardware accelerated STM; HybridTM -
EazyHTM: Eager-Lazy Hardware Transactional Memory
Keyword: EazyHTM; Decoupled conflict resolution and detection
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