Top Posts

• [Top] Feb 12, 2023

  Understanding Redis Source Code

• [Top] Nov 20, 2022

  Cheat Sheet for Building and Deploying SPEC

• [Top] Mar 9, 2022

  QEMU Cheat Sheet for Full-System Simulation

• [Top] Jan 22, 2020

  Understanding Discrete Event Contention Simulation in zSim

• [Top] Jan 9, 2020

  Understanding Cache Coherence Concurrency Control Protocol in zSim

• [Top] Jan 1, 2020

  Understanding Processor Microarchitecture Simulation in zSim

• [Top] Dec 25, 2019

  Understanding Cache System Simulation in zSim

• [Top] Mar 16, 2018

  Adding Dynamic Github Contribution Calendar To Your Static Page

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Posts

• [Paper Review] Dec 16, 2022 , Paper published in MICRO 2022

  Translation-optimized Memory Compression for Capacity

  Keyword: Memory Compression; TMCC; Deflate
• [Paper Review] Dec 11, 2022 , Paper published in MICRO 2022

  DaxVM: Stressing the Limits of Memory as a File Interface

  Keyword: Virtual Memory; NVM; mmap
• [Post] Nov 20, 2022

  Cheat Sheet for Building and Deploying SPEC

• [Paper Review] Aug 11, 2022 , Paper published in MEMSYS 2018

  Cocoa: Synergistic Cache Compression and Error Correction in Capacity Sensitive Last Level Caches

  Keyword: Cache Compression; BDI; ECC
• [Paper Review] Aug 9, 2022 , Paper published in ICCD 2017

  Dual Dictionary Compression for the Last Level Cache

  Keyword: Cache Compression; Dictionary Compression

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