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• [Top] Feb 12, 2023

  Understanding Redis Source Code

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  Cheat Sheet for Building and Deploying SPEC

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  QEMU Cheat Sheet for Full-System Simulation

• [Top] Jan 22, 2020

  Understanding Discrete Event Contention Simulation in zSim

• [Top] Jan 9, 2020

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• [Top] Jan 1, 2020

  Understanding Processor Microarchitecture Simulation in zSim

• [Top] Dec 25, 2019

  Understanding Cache System Simulation in zSim

• [Top] Mar 16, 2018

  Adding Dynamic Github Contribution Calendar To Your Static Page

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Posts

• [Paper Review] Jun 10, 2018 , Paper published in ISCA 2016

  Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures

  Keyword: BPC; Compression; Bit Plane
• [Paper Review] Jun 9, 2018 , Paper published in ISCA 2013

  Efficient virtual memory for big memory servers

  Keyword: Direct Segment; Segmentation
• [Paper Review] Jun 2, 2018 , Paper published in ASPLOS 2018

  Hardware Multithreaded Transactions

  Keyword: Thread Level Speculation; MOESI; Coherence; HMTX
• [Paper Review] May 31, 2018 , Paper published in LNCS 2008

  Maintaining Consistent Transactional States without a Global Clock

  Keyword: TL2; STM; Global Clock; Thread Local Counter
• [Paper Review] May 30, 2018 , Paper published in SPAA 2013

  Reduced hardware transactions: a new approach to hybrid transactional memory

  Keyword: Reduced HTM; Hybrid TM; TL2; RH1; RH2

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